`timescale 1ns / 1ps

module sim_adder;

	reg A0,A1,A2,A3,B0,B1,B2,B3,Cin;
	wire S0,S1,S2,S3,Cout;
	
	xmjadder4bit uut(
		.A0(A0),
		.A1(A1),
		.A2(A2),
		.A3(A3),
		.B0(B0),
		.B1(B1),
		.B2(B2),
		.B3(B3),
		.Cin(Cin),
		.S0(S0),
		.S1(S1),
		.S2(S2),
		.S3(S3),
		.Cout(Cout));
	
	integer i;
	initial begin
		Cin=0;
		{A3,A2,A1,A0}=0;
		{B3,B2,B1,B0}=1;
		for(i=1;i<7;i=i+1) begin
			#100;
			{A3,A2,A1,A0}={B3,B2,B1,B0};
			{B3,B2,B1,B0}={S3,S2,S1,S0};
		end
	end
endmodule

